Silicon wafer with embedded optoelectronic material for monolithic OEIC

ABSTRACT

A structure with an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO 2 . Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 μm), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).

PRIORITY INFORMATION

[0001] This application claims priority from provisional applicationSer. No. 60/223,407 filed Aug. 4, 2000.

BACKGROUND OF THE INVENTION

[0002] The invention relates to an epitaxial structure that containsoptoelectronic material embedded in Si, such that the entire wafer canbe processed using traditional Si CMOS tools to create a true monolithicoptoelectronic integrated circuit (OEIC).

[0003] It has been a long-standing desire of the microelectronics andtelecommunications industries to combine optoelectronic components withSi circuitry. Adding optoelectronic functionality to standard Siintegrated circuits (ICs) would enable a tremendous range of newapplications and devices, such as on-chip optical communication(enabling optical clock timing for high speed processors), inter-chipoptical communication links (optical interconnects), and more efficientand compact optical transceivers for data communications andtelecommunications.

[0004] Although hybrid integration of optical components with Si ICsprovides a possible solution, this is not the preferred solution. Truemonolithic integration of optoelectronics with Si circuitry is farsuperior to hybrid integration for several reasons. Monolithicintegration yields more compact devices (and therefore higher deviceintegration densities); lower packaging costs since wire bonds orflip-chip bonds between the optoelectronic component and Si IC necessaryin hybrid integration schemes are eliminated; lower processing costssince the entire device can be processed using standard Si CMOStechniques; and improved device characteristics in applications wherehybrid integration yields undesirable electrical parasitics.

[0005] It is therefore desirable to create a truly monolithic structurecontaining both optoelectronic functionality and Si CMOS circuitry.However, an intrinsic problem with integrating optoelectronicfunctionality into Si chips is that Si itself is not a goodoptoelectronic material as it neither emits nor detects lightefficiently. Therefore, the optically active material integrated withthe Si CMOS circuitry must be something other than Si, such as Ge, SiGe,GaAs, InP, AlGaAs, InGaAs, InGaAsP, or any other optically active groupIV or III-V semiconductor material. Due to the large lattice mismatchand thermal expansion coefficient mismatch between these materials andSi, monolithically integrated devices created until now have beenperformance limited by the resulting crystalline defects (specificallythreading dislocations) from epitaxy. However, recent progress in defectfiltering schemes, such as graded buffer layers or selective epitaxialgrowth and epitaxial lateral overgrowth, has overcome this problem andenabled the creation of lattice-mismatched epitaxial layers of suitablequality for optoelectronic devices, such as photodetectors, lightemitting diodes (LEDs), and lasers.

[0006] A major limitation of monolithic optoelectronic integratedcircuits created until now has been the requirement that all Si CMOSprocessing steps be fully completed before integration of the opticallyactive material. This requirement has existed because Si CMOS processingtools cannot be exposed to any other materials due to contaminationconcerns.

SUMMARY OF THE INVENTION

[0007] It is therefore an object of the invention to provide anepitaxial structure in which an optically active material is embeddedwithin Si such that the entire wafer can be processed using traditionalSi CMOS tools to yield a true monolithic optoelectronic integratedcircuit. It is also an object of the invention to provide a method bywhich such a wafer structure may be obtained.

[0008] The invention provides a structure in which the optically activelayer is embedded in a Si wafer, such that the outermost epitaxial layerexposed to the CMOS processing equipment is always Si (or anotherCMOS-compatible material such as SiO₂). Since the optoelectronic layeris completely surrounded by Si, the wafer is fully compatible withstandard Si CMOS manufacturing. Therefore, all of the manufacturing andcost benefits associated with Si CMOS processing are fully realized bythe invention.

[0009] It is important to note that embedding the optoelectronic layerin Si does not prevent transmission of optical signals between the OEICand an external waveguide (such as an optical fiber) or free space.Specifically, for wavelengths of light longer than the bandgap of Si(1.1 μm), Si is completely transparent and therefore optical signals canbe transmitted between the embedded optoelectronic layer and an externalwaveguide using either normal incidence (through the Si substrate or topSi cap layer) or in-plane incidence (edge coupling). This providestremendous flexibility in designing an OEIC used for the typicaltelecommunications wavelengths of 1.3 and 1.55 μm. Additionally, evenwavelengths shorter than the bandgap of Si can be coupled in and out ofthe embedded optoelectronic layer. This is because the top Si cap layercan be made thin enough that it is only minimally absorbing at othercommonly used wavelengths, such as 980 or 850 nm. Alternatively, edgecoupling could be used for these wavelengths. This flexibilityfacilitates design of complex system-on-a-chip structures where multiplewavelengths and/or multiple optical in/out connections are required.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIGS. 1A-1D are block diagrams of an exemplary embodiment of agraded buffer/wafer bonding process to create an optically-active layerembedded in a Si wafer in accordance with the invention;

[0011] FIGS. 2A-2D are block diagrams of another exemplary embodiment ofa graded buffer/wafer bonding process to create a more complex waferstructure that contains an insulating layer between the optically-activelayer and the Si substrate;

[0012] FIGS. 3A-3D are block diagrams of yet another exemplaryembodiment of a graded buffer/wafer bonding process to create a yet morecomplex wafer structure that contains a Si contact layer between theinsulating layer and optically-active layer;

[0013]FIG. 4 are block diagrams showing the resulting wafer structure ofstill yet another exemplary embodiment of a graded buffer/wafer bondingprocess, wherein the optically-active layer is isolated from both the Sisubstrate and the Si cap layer by insulating layers, and showing apossible implementation of the Si CMOS electronics to create amonolithic optoelectronic integrated circuit;

[0014] FIGS. 5A-5C are block diagrams of an exemplary embodiment of agraded buffer/wafer bonding process where the original substrate andgraded buffer layer are not removed from the structure;

[0015] FIGS. 6A-6C are block diagrams showing an exemplary embodiment ofan OEIC processing such that the Si CMOS electronics are located in theSi substrate below the optically-active layer; and

[0016]FIG. 7 is a block diagram of an exemplary embodiment of an OEICimplementation in which emitters, detectors, and Si CMOS electronicshave all been monolithically integrated on the same Si substrate.

DETAILED DESCRIPTION OF THE INVENTION

[0017] There are several different techniques available tomonolithically integrate lattice-mismatched materials, including waferbonding, graded buffer layers, and epitaxial lateral overgrowth. Waferbonding is an attractive option because it can directly combine twodissimilar materials together without the need for an “interlayerstructure”, e.g., a graded buffer layer or selective epitaxial mask.However, even though wafer bonding eliminates the lattice-mismatchproblem, two new problems arise which have prevented wafer bonding fromreaching its full potential: thermal expansion mismatch and wafer sizemismatch.

[0018] Thermal expansion mismatch is a serious issue when the dissimilarwafers being bonded are of similar thickness. This mismatch can causelarge strains to develop during heating and cooling that can crack theassembly or cause the wafers to debond. Wafer size mismatch relates tothe fact that two dissimilar wafers being bonded typically havedifferent diameters. Therefore, some fraction of the larger diameterwafer is wasted. For example, consider bonding a Si substrate and a Gesubstrate. Si substrates are commonly available in an eight-inchdiameter, while Ge is commonly available only four inches in diameter.Therefore, only a portion of the Si substrate would be covered by thebonding process, while the rest of the wafer would be wasted.

[0019] The combination of graded layer growth and wafer bonding removesthese two problems and provides tremendous flexibility to create newintegrated semiconductor platforms on Si substrates. Consider again theexample of bonding Ge to Si, this time using the graded layer/waferbonding technique illustrated in FIGS. 1A-1D. In this technique, agraded SiGe layer 102 (graded from 0-100% Ge) is epitaxially grown on aSi substrate 100 of any diameter. A Ge layer 104 is then grown on theSiGe graded layer 102. In order to reduce surface roughness, aplanarization step such as chemical mechanical polishing can be insertedduring growth of the SiGe graded layer 102, as described in U.S. Pat.No. 6,107,653, incorporated herein by reference. Also note that any ofthe layers described in this invention can receive planarization steps,if desired.

[0020] The wafer can then be bonded to another Si substrate 106, of thesame diameter as shown in FIGS. 1A and 1B. This technique thereforeeliminates the wafer size mismatch issue, and it also eliminates thethermal mismatch issue because both wafers are essentially Si.

[0021] Once the wafers are bonded, the original Si substrate 100 canthen be ground and selectively etched back. In one embodiment (shown inFIG. 1C), the SiGe graded layer 102 can also be completely removed toleave only the Ge layer 104 on the new host Si substrate 106. A Si caplayer 108 can now be epitaxially grown on top of this structure, suchthat the optically-active layer 104 (Ge in this case) is effectivelyembedded in a Si wafer as shown in FIG. 1D.

[0022] Although the large lattice mismatch (about 4%) between Ge and Siwill create many dislocations during this final Si deposition, they willonly reside in the Si cap layer 108, and will not penetrate into theoptoelectronic Ge layer 104. This is because for systems with a largelattice mismatch (typically greater than 1.5%) the growth mode is suchthat dislocations can only achieve short glide distances and thereforewill remain in the deposited film. Penetration of misfit dislocationsinto the underlying film layer (Ge in this case) requires longdislocation glide distances typically only achieved for systems with alattice mismatch <1.5%. These dislocations in the Si cap layer 108 willnot have a deleterious effect on device operation if the CMOSelectronics are located in the Si substrate 106 (see FIGS. 6A-6C),rather than in the Si cap layer 108.

[0023] In another embodiment, a Si cap layer could be wafer bonded (fromanother Si substrate) on top of the optically active layer, rather thanepitaxially grown. In this embodiment, the Si cap layer would be of highquality, and therefore could be processed into CMOS circuits containingfield effect transistors (FETs) or similar devices. In yet anotherembodiment, the original SiGe graded layer 102 could be only partiallyremoved during etch back, such that a strained Si cap layer could beepitaxially grown on top of the remaining SiGe graded layer 102. Thisstrained Si cap layer would be of high quality, and could be processedinto CMOS circuits with enhanced performance compared to relaxed Si CMOScircuits. In still yet another embodiment, the original Si substrate 100and SiGe graded layer 102 could be completely removed, and a uniformcomposition SiGe layer could be wafer bonded on top of the opticallyactive layer. A strained Si cap layer could then be epitaxially grown onthis SiGe layer and could be processed into CMOS circuits.

[0024] It will be appreciated by those skilled in the art thattechniques other than grinding/etch back, such as delamination, can beused to remove the Si substrate 100 and graded SiGe layer 102 from thefirst wafer.

[0025] It will also be appreciated by those skilled in the art thatadditional layers could potentially be incorporated into the structure.For example, in another embodiment as illustrated in FIGS. 2A-2D, afirst Si substrate 200 can have a 0-100% graded SiGe layer 202 with a Gelayer 204 on top as before, while a second Si substrate 206 can have athick insulating layer 208 on its surface, such as SiO₂. This insulatinglayer will serve to isolate the optoelectronic layer 204 from the Sisubstrate 206 (and any CMOS electronics subsequently processed in saidsubstrate). A (highly defective) Si layer 210 can again be deposited ontop of the optoelectronic layer 204.

[0026] In yet another embodiment as illustrated in FIGS. 3A-3D, after agraded SiGe 300 and Ge layers 302 are grown on a first Si substrate 304,a Si cap layer 306 can be grown on the Ge layer 302. An optional SiO₂layer can then be grown or deposited on this Si cap layer to aid inwafer bonding. Although this Si cap layer 306 will have a high densityof dislocations, they will not deleteriously affect device performancesince this Si layer 306 will not be active optically or electronically.One benefit of including this Si cap layer 306 in the heterostructure isto serve as an etch stop when forming the bottom contact to the Ge layer302. This wafer can then be bonded to another Si substrate 308 which hasan insulating layer 310, such as SiO₂, on it as before. After etchingback to the Ge layer 302, another Si cap layer 312 can be provided.

[0027] In still yet another embodiment as illustrated in FIGS. 4A-4B, aninsulating layer 400 can be inserted between a top Si cap layer 402 andan optically active layer 404. This would be useful to isolate theoptically-active layer 404 from the CMOS electronics in a particularOEIC embodiment where the CMOS electronics were located in the top Sicap layer 402, rather than in the Si substrate 408.

[0028] As shown in FIGS. 5A-5C, it is also possible to have anembodiment in which an original Si substrate 500 is not removed. Onesuch structure would involve growing a graded SiGe layer (graded 0-100%)502, and then a uniform Ge layer 504 as the optically active layer. Asecond Si substrate 506 with a SiO₂ layer 508 can then be wafer bondedon top of the Ge layer 504. The second Si substrate 506 can then bepartially etched-back or delaminated to leave a thin Si cap layer 510,which is substantially defect-free. The cap layer 510 can besubstantially defect-free. The CMOS electronics would be processed intoa top Si cap layer 510 in this embodiment. Additional layers could alsobe included in this embodiment as discussed above, such as a relaxedSiGe layer with a strained Si cap layer for strained Si CMOS.

[0029] It is to be understood that additional layers that serve variouspurposes could be included in the structure. For example, layers couldbe included at various heterointerfaces to minimize the (possiblydeleterious) effect of energy band discontinuities at theseheterointerfaces. As another example, quarter-wavelength-thick layers ofmaterials of alternating high- and low-refractive index could be grownor deposited on top of either wafer before bonding such that ahigh-reflectance multilayer stack would exist below the optoelectronicmaterial. This stack could serve as the lower mirror of a resonantcavity to enhance optical responsivity at a particular wavelength.During subsequent processing of the bonded wafers, a high-reflectancemirror could be deposited above the optoelectronic layer to complete theresonant cavity, or the uppermost ambient/semiconductor interface couldserve as the top mirror.

[0030] The structures and techniques described are extendable to otheroptoelectronic materials besides Ge. For example, simply by grading theSiGe graded layer on the first Si substrate to a certain compositionless than 100% Ge, and then growing a uniform layer of SiGe at thatcomposition, a SiGe layer of that composition could be embedded in a Siwafer as the optically-active layer.

[0031] As another example, through compositional grading of SiGe andInGaAs layers on Si, it is possible to create a bonded layer of InP orInGaAs on Si as well. This can be accomplished as follows. First, agraded SiGe epitaxial layer (graded from 0-100% Ge) is epitaxially grownon a Si substrate. Since GaAs and Ge have nearly equal latticeconstants, a GaAs layer can then be epitaxially grown on top of the Gelayer. At this point, the GaAs layer can be wafer bonded to another Sisubstrate such that the embedded active optoelectronic layer was GaAs.Alternatively, a relaxed, graded InGaAs layer can be grown on the GaAslayer, graded from 0% In to some desired In concentration, as describedin U.S. Pat. No. 6,232,138, incorporated herein by reference. The InGaAslayer can be wafer bonded to another Si substrate.

[0032] In yet another embodiment, InGaAsP or InP lattice-matched toIn_(0.53)Ga₀ ₄₇As can be grown on the structure and wafer bonded toanother Si substrate. In yet a more complicated embodiment,lattice-matched heterostructures for various optoelectronic devices canbe epitaxially grown on the first wafer, and wafer bonded to the secondSi substrate.

[0033] As an example, a relaxed SiGe graded layer can be grown from0-100% Ge on the first Si substrate, on top of which a relaxed, gradedInGaAs layer can then be grown from 0-53% In. A lattice-matched InPlayer could then be grown, and serve as the starting substrate for anyoptoelectronic device lattice-matched to InP. For example, a laserstructure containing InP, InGaAs, and InGaAsP, all lattice-matched toInP, can then be grown. The entire device structure can be wafer bondedto a second Si substrate, such that the embedded optoelectronic layer inthis case was an entire laser (or LED or detector) structure, ratherthan a single layer as described with Ge. Of course, the structure wouldhave to be grown “upside-down” on the original Si substrate since itwould be inverted upon being wafer bonded to the second Si substrate.Similarly, an entire heterostructure lattice-matched to GaAs could begrown on the first Si substrate and then wafer bonded to the second Sisubstrate.

[0034] These other optoelectronic layers can also be coated with Si,such that the embedded optically-active semiconductor material can bechosen from a wide range of materials, including: Ge, SiGe, GaAs,AlGaAs, InGaAs, InP, InGaAsP, any III-V alloy lattice-matched to GaAs,any III-V alloy lattice-matched to InP, any multiple-layerheterostructure (a laser, light emitting diode, or photodetector)lattice-matched to GaAs, or any multiple-layer heterostructurelattice-matched to InP.

[0035] Once the planar composite wafer has been fabricated, it containsat a minimum a Si substrate, a layer of optically active material, and aSi cap layer. It may also include optional additional layers or deviceheterostructures as described. This structure can be processed to createa monolithic optoelectronic integrated circuit. For example, considerthe case of creating an optical receiver circuit on Si. The opticalreceiver could contain a detector and receiver circuit, or multipledetectors and a receiver circuit(s). Since the optically active layer iscompletely embedded in a Si wafer, this planar composite wafer can beprocessed as a normal Si wafer would be for CMOS manufacturing.

[0036] In one embodiment as illustrated in FIGS. 6A-6C, a starting waferheterostructure 600 based on the resulting structure shown in FIG. 3D,Si CMOS electronics 602 can be processed on the Si substrate. In thisembodiment, an early step would include patterning the wafer to definethe optoelectronic receiver areas, and these areas would be protectedwith a mask. The other areas would be etched down to the Si substrate,leaving a virgin Si surface to be processed into CMOS electronics.

[0037] It is expected that special attention may be required for theCMOS processing thermal budget to minimize the interdiffusion of (andmaintain the integrity of) the embedded optoelectronic layer. However,the thermal budget and controlled interdiffusion could also be used tothe device designer's advantage. For example, a slight interdiffusion atthe upper and lower surfaces of the optically-active layer (Ge in thisexample) would grade these interfaces and therefore minimize sharpenergy band discontinuities that might be deleterious for certaindevices. After CMOS processing is complete, the areas with Ge can thenbe processed into detectors, and final interconnections can be madebetween the Si CMOS circuit and the Ge detectors.

[0038] Alternatively, in another embodiment shown in FIG. 4D, the SiCMOS electronics can also be fabricated above the optoelectronic layer,rather than co-planar with it. Rather than epitaxially growing ahighly-defective Si cap layer above the optoelectronic (Ge in thisexample) layer, a high-quality Si cap layer can be wafer bonded abovethe optoelectronic layer as described. The Si CMOS electronics can beformed in this Si cap layer above the optoelectronic layer, rather thanin the Si substrate. Vias can be drilled through this top Si CMOS layerto provide contacts to the underlying optoelectronic layer wheredesired. Underlying Si layers could serve as etch stops, as mentionedabove. Individual components can be isolated from one another usingtrench isolation.

[0039] In yet another embodiment, the CMOS circuits can be fabricated ina strained Si cap layer above the optoelectronic layer as described,rather than in a relaxed Si cap layer. This can be achieved by waferbonding (or epitaxially growing) a relaxed SiGe layer of a desiredcomposition on top of the optoelectronic (Ge) layer. A strained Si caplayer can then be epitaxially grown on top of the relaxed SiGe layer.Again, vias can be drilled through the strained Si and relaxed SiGelayers to contact the optoelectronic layer where desired.

[0040] The optoelectronic layer being embedded in Si has severaladvantages. First, the entire integration sequence can occur within a Sifoundry. Even the interconnects between the Si CMOS and optoelectroniclayer can be performed with Si contact technology, since the contactwhich will be formed in the optoelectronic region will be a contact tothe Si cap layer on the optoelectronic layer. All contact andinterconnect materials could be based on standard Si VLSI processing.For example, contacts could be made using Ni, Co, or Ti, and theresulting silicides. Via plugs can use tungsten, while metalinterconnect lines can use Al or Cu. Also, the large defect density inthe Si contact layers (present in certain embodiments) will aid increating low resistance contacts, since these defects will enhanceinterdiffusion and diffusion.

[0041] Alternatively, since the Si layers are deposited epitaxially insome embodiments, the doping can be controlled with epitaxy and highthermal budgets for activating implants are not needed in theseembodiments. Additionally, Ge-based optically active regions do notnecessarily need to be doped during the epitaxial process. Since Ge isisoelectronic with Si, the same elements that dope Si will dope Ge.Thus, given the current process simulation tools, one can simply dopethe Si contact layers (in certain embodiments where the Ge layerdirectly contacts a Si layer at its upper and lower surfaces, i.e. FIG.3D) and leave the Ge intrinsic; during subsequent processing, thedopants can enter the Ge, creating the p-i-n structure in Ge needed forphotodiode behavior. Also, in situ deposition of a Si layer on top ofthe Ge will help prevent the surface nucleation of cracks in the Ge dueto the thermal expansion difference between Si and Ge.

[0042] Finally, it is important to note that since Si has a largerbandgap than the optical wavelengths of light typically used intelecommunications (1.3 and 1.55 μm), the Si substrate and top cap layerare both transparent to these wavelengths. Thus, transmission of opticalsignals between the embedded optoelectronic layer and an externalwaveguide (such as an optical fiber or free space) can easily occur byeither normal incidence through the front or backside of the wafer, orin-plane incidence. Additionally, even wavelengths shorter than thebandgap of Si can be coupled in and out of the embedded optoelectroniclayer. This is because the top Si cap layer can be made thin enough thatit is only minimally absorbing at other commonly used wavelengths, suchas 980 or 850 nm. Alternatively, edge coupling could be used for thesewavelengths.

[0043] Thus, the embedded optically-active layers can be used for thecreation of complex integrated optoelectronic transceivers. One cantherefore construct, for example, optical network switches on a chip. Aschematic example of such an OEIC 700 is shown in FIG. 7. In thisexample, an InGaAs/InP heterostructure has been embedded in a Si wafer702. Certain regions have been processed to form emitters 704 using thisembedded optically-active material, while other regions have beenprocessed to form detectors 706. The diagram has been drawnsimplistically for clarity, as the InGaAs/InP emitters and detectors arenot actually exposed on the surface of the wafer. They are embedded inthe wafer 702. The top layer of the entire structure is Si.

[0044] A simple structure that would enable the formation of bothemitters and detectors is a p-i-n structure, which would emit light whenforward-biased, and detect light when reverse-biased. In another regionof the wafer, Si electronics 708 have been processed into the Sisubstrate. The Si electronics are connected to the optoelectronicdevices using interconnects based on standard Si interconnect materials,such as Al or Cu. Additionally, since the entire top surface of thewafer is a Si cap layer, the contacts to the optoelectronic emitters anddetectors can be made using standard Si contact materials, such as Ni,Co, or Ti silicides. Finally, optical signals can be transmitted betweenthe OEIC and external optical fibers. One possibility is shown in thefigure, where the light is transmitted through the substrate tobutt-coupled fibers 710. The optical signals could also be transmittedthrough the Si cap layer, such that optical fibers would be positionedabove the OEIC. A third possibility is to use edge coupling, wherev-grooves would be etched in the substrate to align optical fibers forin-plane incidence.

[0045] Although the present invention has been shown and described withrespect to several preferred embodiments thereof, various changes,omissions and additions to the form and detail thereof, may be madetherein, without departing from the spirit and scope of the invention.

What is claimed is:
 1. A semiconductor heterostructure comprising: a Sisubstrate; an optically active semiconductor material on said substrate,said optically active semiconductor material being lattice mismatchedwith respect to said substrate and substantially relaxed; and a caplayer on said optically active semiconductor material, said cap layercomprising Si.
 2. The heterostructure of claim 1, wherein said opticallyactive semiconductor material comprises material from the group of: Ge,GaAs, InP, AlGaAs, InGaAs, InGaAsN, InGaAsP, a III-V alloylattice-matched to GaAs, or a III-V alloy lattice-matched to InP.
 3. Theheterostructure of claim 1, wherein said optically active semiconductormaterial comprises SiGe.
 4. The heterostructure of claim 1, wherein saidoptically active semiconductor material comprises a multiple layerheterostructure lattice-matched to GaAs, or a multiple layerheterostructure lattice-matched to InP.
 5. The heterostructure of claim1, wherein said optically active semiconductor material has a smallerbandgap than the bandgap of Si.
 6. The heterostructure of claim 1,wherein said cap layer is monocrystalline and substantially defect-free.7. The heterostructure of claim 1, wherein said cap layer ismonocrystalline and highly defective.
 8. The heterostructure of claim 1further comprising a relaxed, graded Si_(1−x)Ge_(x) layer graded fromx=0 to x≦1, positioned between said Si substrate and said opticallyactive semiconductor material.
 9. The heterostructure of claim 8 furthercomprising a relaxed, graded In_(x)Ga_(1−x)As layer graded from x=0 tox≦1, positioned between said relaxed, graded Si_(1−x)Ge_(x) layer andsaid optically active semiconductor material.
 10. The heterostructure ofclaim 1, wherein at least one layer has been planarized.
 11. Asemiconductor heterostructure comprising: a Si substrate; an insulatinglayer on said substrate; an optically active semiconductor material onsaid insulating layer, said optically active semiconductor materialbeing lattice mismatched with respect to said substrate andsubstantially relaxed; and a cap layer on said optically activesemiconductor material, said cap layer comprising Si.
 12. Theheterostructure of claim 11, wherein said optically active semiconductormaterial comprises material from the group of: Ge, GaAs, InP, AlGaAs,InGaAs, InGaAsN, InGaAsP, a III-V alloy lattice-matched to GaAs, or aIII-V alloy lattice-matched to InP.
 13. The heterostructure of claim 11,wherein said optically active semiconductor material comprises SiGe. 14.The heterostructure of claim 11, wherein said optically activesemiconductor material comprises a multiple layer heterostructurelattice-matched to GaAs, or a multiple layer heterostructurelattice-matched to InP.
 15. The heterostructure of claim 11, whereinsaid optically active semiconductor material has a smaller bandgap thanthe bandgap of Si.
 16. The heterostructure of claim 11, wherein saidinsulating layer is SiO₂.
 17. The heterostructure of claim 11, whereinsaid cap layer is monocrystalline and substantially defect-free.
 18. Theheterostructure of claim 11, wherein said cap layer is monocrystallineand highly defective.
 19. The heterostructure of claim 11, wherein atleast one layer has been planarized.
 20. A semiconductor heterostructurecomprising: a Si substrate; an optically active semiconductor materialon said substrate, said optically active semiconductor material beinglattice mismatched with respect to said substrate and substantiallyrelaxed; an insulating layer on said optically active semiconductormaterial; and a cap layer on said insulating layer, said cap layercomprising Si.
 21. The heterostructure of claim 20, wherein saidoptically active semiconductor material comprises material from thegroup of: Ge, GaAs, InP, AlGaAs, InGaAs, InGaAsN, InGaAsP, a III-V alloylattice-matched to GaAs, or a III-V alloy lattice-matched to InP. 22.The heterostructure of claim 20 wherein said optically activesemiconductor material comprises SiGe.
 23. The heterostructure of claim20, where said optically active semiconductor material comprises amultiple layer heterostructure lattice-matched to GaAs, or a multiplelayer heterostructure lattice-matched to InP.
 24. The heterostructure ofclaim 20, wherein said optically active semiconductor material has asmaller bandgap than the bandgap of Si.
 25. The heterostructure of claim20, wherein said insulating layer comprises SiO₂.
 26. Theheterostructure of claim 20, wherein said cap layer is monocrystallineand substantially defect-free.
 27. The heterostructure of claim 20further comprising a relaxed, graded Si_(1−x)Ge_(x) layer graded fromx=0 to x≦1, positioned between said Si substrate and said opticallyactive semiconductor material.
 28. The heterostructure of claim 27further comprising a relaxed, graded In_(x)Ga_(1−x)As layer graded fromx=0 to x≦1, positioned between said relaxed, graded Si_(1−x)Ge_(x) layerand said optically active semiconductor material.
 29. Theheterostructure of claim 20, wherein at least one layer has beenplanarized.
 30. A semiconductor heterostructure comprising: a Sisubstrate; a first insulating layer on said substrate; an opticallyactive semiconductor material on said first insulating layer, saidoptically active semiconductor material being lattice mismatched withrespect to said substrate and substantially relaxed; a second insulatinglayer on said optically active semiconductor material; and a cap layeron said second insulating layer, said cap layer comprising Si.
 31. Theheterostructure of claim 30, wherein said optically active semiconductormaterial comprises material from the group of: Ge, GaAs, InP, AlGaAs,InGaAs, InGaAsN, InGaAsP, a III-V alloy lattice-matched to GaAs, or aIII-V alloy lattice-matched to InP.
 32. The heterostructure of claim 30,wherein said optically active semiconductor material comprises SiGe. 33.The heterostructure of claim 30, wherein said optically activesemiconductor material comprises a multiple layer heterostructurelattice-matched to GaAs, or a multiple layer heterostructurelattice-matched to InP.
 34. The heterostructure of claim 30, whereinsaid optically active semiconductor material has a smaller bandgap thanthe bandgap of Si.
 35. The heterostructure of claim 30, wherein saidinsulating layers comprise SiO₂.
 36. The heterostructure of claim 30,wherein said cap layer is monocrystalline and substantially defect-free.37. The heterostructure of claim 30, wherein at least one layer has beenplanarized.
 38. A semiconductor heterostructure comprising: a Sisubstrate; a first insulating layer on said substrate; a first Si layeron said first insulating layer; an optically active semiconductormaterial on said first Si layer, said optically active semiconductormaterial being lattice mismatched with respect to said substrate andsubstantially relaxed; a second Si layer on said optically activesemiconductor material; a second insulating layer on said second Silayer; a cap layer on said second insulating layer, said cap layercomprising Si.
 39. The heterostructure of claim 38, wherein saidoptically active semiconductor material comprises material from thegroup of: Ge, GaAs, Inp, AlGaAs, InGaAs, InGaAsN, InGaAsP, a III-V alloylattice-matched to GaAs, or a III-V alloy lattice-matched to InP. 40.The heterostructure of claim 38, wherein said optically activesemiconductor material comprises SiGe.
 41. The heterostructure of claim38, wherein said optically active semiconductor material comprises amultiple layer heterostructure lattice-matched to GaAs, or a multiplelayer heterostructure lattice-matched to InP.
 42. The heterostructure ofclaim 38, wherein said optically active semiconductor material has asmaller bandgap than the bandgap of Si.
 43. The heterostructure of claim38, wherein said insulating layers comprise SiO₂.
 44. Theheterostructure of claim 38, wherein said Si layers are monocrystallineand highly defective.
 45. The heterostructure of claim 38, wherein saidcap layer is monocrystalline and substantially defect-free.
 46. Theheterostructure of claim 38, wherein at least one layer has beenplanarized.
 47. The heterostructure of claim 1, wherein said cap layercomprises a relaxed SiGe layer with a strained Si cap layer.
 48. Theheterostructure of claim 11, wherein said cap layer comprises a relaxedSiGe layer with a strained Si cap layer.
 49. The heterostructure ofclaim 20, wherein said cap layer comprises a relaxed SiGe layer with astrained Si cap layer.
 50. The heterostructure of claim 30, wherein saidcap layer comprises a relaxed SiGe layer with a strained Si cap layer.51. The heterostructure of claim 38, wherein said cap layer comprises arelaxed SiGe layer with a strained Si cap layer.